A two-chip interface for a MEMS accelerometer

descriptionPublicationkeyboard_double_arrow_right Article 01 Aug 2002Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Instrumentation and Measurement, volume 51, pages 853-858 (issn: 0018-9456, eissn: 1557-9662,

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Authors: Tetsuya Kajita; Un-Ku Moon; Gabor C. Temes;

doi: 10.1109/tim.2002.803508

A two-chip interface for a MEMS accelerometer

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Abstract

A proposed third-order noise-shaping accelerometer interface circuit enhances the signal-to-noise ratio, compared with previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled correlated double sampling integrator is proposed. This scheme functions even with large parasitic capacitances between the sensor and the interface circuit. The op-amp noise is first-order shaped. Dithering circuit is also implemented on the chip, fabricated in an 1.6-/spl mu/m CMOS process.

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