Developing safety-aware designs on field programmable gate arrays (FPGA) directly feeds a demand for error emulation techniques. Since for SRAM-based FPGA single event upsets (SEU) are the most important concern, error testing is usually executed using error injection into the configuration memory. This error injection is typically done with either external or internal injection with the corresponding drawback of slow injection speeds or inaccurate results due to injection side effects. In this context, this work introduces a complete test flow with a mathematical framework and injection parameters which allow balancing the tradeoff between quality of the results and injection speed. An implementation of this flow is presented and executed on a case study based on an AES encryption application. The flows implementation has a very low resource overhead, which can be almost negligible in some instances. Therefore, it can be included in a final implementation allowing for robustness measurements of the finally placed and routed design.