Clock gating is widely used in modern integrated circuits as a means of reducing dynamic power consumption. In this paper we present a comprehensive analysis of the impact of clock gating during test. We then propose a new type of test point called Clock Gate Test Points. Similar to classic test point techniques, clock gate test points help in increasing the test coverage as well as reducing the number of test patterns and thus test time. We also outline techniques for applying the proposed test points in a design. We present the results of coverage improvement and test pattern reduction with the proposed method for several large industrial circuits. Our results show that with the proposed method, in many cases, more than 2.0% improvement in transition delay fault coverage can be achieved and the number of test patterns can be reduced by more than 50% for the same fault coverage. Furthermore, the proposed test points add very little area overhead and do not impact the circuit performance.