Conventional ASIC test compression techniques cannot be used for FPGAs due to the lack of unspecified bits in FPGA test configuration data. Also, majority of FPGA test time and volume is due to test configurations rather than test patterns. Hence, without proper test configuration compression techniques, excessively large test data volume and load time can adversely affect FPGA test costs. In this paper, we present a novel solution for FPGA test configuration compression by exploiting the inherent regularity of FPGAs in generating compressible test configurations. Depending on the size of the FPGA device, 7.3x ? 117x compression ratio can be achieved for interconnect test configurations generated for Xilinx Virtex FPGAs.