In modern SoCs embedded memories include the large majority of defects. In addition defect types are becoming more complex and diverse and may escape detection during fabrication test. As a matter of fact memories have to be tested by test algorithms achieving very high fault coverage. Fixing the test algorithm during the design phase may not be compatible with this goal, as thorough screening inspection or customer returns may discover after fabrication unexpected fault types. A programmable BIST approach allowing selecting after fabrication a vast variety of memory tests is therefore desirable, but may lead to unacceptable area cost. In this work we present a programmable memory BIST architecture offering such flexibility at an area cost similar to traditional memory BIST schemes