Simulation of transients caused by single-event upsets in combinational logic

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 06 Feb 2006Publisher:IEEEJournal:IEEE International Conference on Test, 2005.

Authors: Kartik Mohanram;

doi: 10.1109/test.2005.1584063

Simulation of transients caused by single-event upsets in combinational logic

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Abstract

A comprehensive technique for simulation of transients caused by single-event upsets (SEUs) in combinational logic circuits is described. Based upon linear RC models of gates, the proposed technique integrates a closed-form model for computation of the SEU-induced transient at the site of a particle strike with propagation models for the transients along a functionally sensitized path. A full set of simulation results indicate that on average, the models are accurate to within 10% of the results obtained using SPICE simulations (peak magnitude and duration about 0.5VDD) with over 1000times improvement in computational speed

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Rice University
United States

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