Summary form only given. In the world of IC testing, efficiency measurements are based on test coverage of modeled faults, often stuck at faults. While this has been effective at the chip level to improve the quality of chip testing, the question is how can this be transferred to the system test level? At the system level we are faced with several potential complications in measuring the quality of the test process. The author discusses two possible techniques to address these complications. In the first technique, we look at what a comprehensive fault model may took like at the system level. The second technique involves a more traditional approach of implementing a test coverage analysis based on functional faults and Failure Mode Effect Analysis (FMEA).