FPGA test and coverage

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 25 Jun 2003Publisher:IEEEJournal:Proceedings. International Test Conference

Authors: Shahin Toutounchi; Andrew Lai;

doi: 10.1109/test.2002.1041811

FPGA test and coverage

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Abstract

This paper presents an FPGA test and coverage methodology. BIST and "shift register" styles of test are discussed. Gate level fault grading results are then presented. Use of an "iterative logic unit" and its impact on test and fault grading is discussed.

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	selected citations These citations are derived from selected sources. This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).	38
	popularity This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.	Average
	influence This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).	Top 10%
	impulse This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.	Top 10%

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Average

Top 10%

Fields of Science

engineering and technology

electrical engineering, electronic engineering, information engineering

Fields of Science

engineering and technology

electrical engineering, electronic engineering, information engineering

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