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Deception by design: fooling ourselves with gate-level models

Authors: Peter C. Maxwell; Jeff Rearick;

Deception by design: fooling ourselves with gate-level models

Abstract

The distortion of test coverage statistics by overly simplistic circuit and fault models is explored. It is shown that the artificially high single stuck-at coverage reported on traditional gate-level models results in the omission of test patterns essential to achieve full coverage. The problem lies not directly with the fault model, but instead with the gate models and test generator assumptions used. The necessity of two-pattern tests is demonstrated on simple library cells, and the stuck-at coverage improvement measured on benchmark circuits is shown to average 33%. The need for a superior fault model is explained.

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Powered by OpenAIRE graph
Found an issue? Give us feedback
selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
4
Average
Top 10%
Top 10%
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