This paper presents a novel logic synthesis and technology mapping approach for Actel-1 MUX-based Field Programmable Gate Arrays (FPGAs) for low power and high performance applications. To deal with functions of large number of variables, decomposed BDD representation has been used. As there is one-to-one correspondence between the BDD representation and the 2-to-l MUX realization, BDD representation allows the use of simple and efficient algorithm for technology mapping to MUX-based FPGAs. Several optimization techniques have been adopted in technology independent and technology mapping phases to minimize area, delay and power dissipation of the realized circuits. Performance of the proposed approach has been compared with the help of experimental results on a large number of ISCAS benchmark circuits.