Silicon-thickness scaling has been used as the main parameter for short-channel-effect (SCE) reduction. Nevertheless, SCEs are still present in advanced thin-layer MOSFETs. Here, for enlarging the insight into SCE suppression, a new compact model is developed based on the SCE origin, which is demonstrated to be the potential distribution at the contact/channel junctions. In addition, it is shown that the potential distribution along the MOSFET channel can be modeled by overlapping potentials coming from the source and drain sides. The developed compact model is verified with leading-edge multi-gate MOSFETs, further demonstrating that device optimization with SCE suppression becomes possible due to the accurate reproduction of the device characteristics. The model validation is done with 2-D device simulations for different channel lengths, oxide, and silicon thicknesses as well as channel-doping concentration, for which an accurate compact-model reproduction is achieved. In addition, the general properties of the potential-based SCE model are extended to other MOSFET device structures.