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image/svg+xml Jakob Voss, based on art designer at PLoS, modified by Wikipedia users Nina and Beao Closed Access logo, derived from PLoS Open Access logo. This version with transparent background. http://commons.wikimedia.org/wiki/File:Closed_Access_logo_transparent.svg Jakob Voss, based on art designer at PLoS, modified by Wikipedia users Nina and Beao IEEE Transactions on...arrow_drop_down
image/svg+xml Jakob Voss, based on art designer at PLoS, modified by Wikipedia users Nina and Beao Closed Access logo, derived from PLoS Open Access logo. This version with transparent background. http://commons.wikimedia.org/wiki/File:Closed_Access_logo_transparent.svg Jakob Voss, based on art designer at PLoS, modified by Wikipedia users Nina and Beao
IEEE Transactions on Electron Devices
Article . 2017 . Peer-reviewed
License: IEEE Copyright
Data sources: Crossref
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Fluctuation Sensitivity Map: A Novel Technique to Characterise and Predict Device Behaviour Under Metal Grain Work-Function Variability Effects

Authors: Guillermo Indalecio; Natalia Seoane; Karol Kalna; Antonio J. Garcia-Loureiro;

Fluctuation Sensitivity Map: A Novel Technique to Characterise and Predict Device Behaviour Under Metal Grain Work-Function Variability Effects

Abstract

A new technique developed for the analysis of intrinsic sources of variability affecting the performance of semiconductor devices is presented. It is based on the creation of a fluctuation sensitivity map (FSM), which supplies spatial information about the source of variability affecting the device performance and reliability, providing useful advice in the development of fluctuation-resistant device architectures. We have applied the FSM to metal grain work-function variations (MGWVs), since they are one of the major contributors to device variability. This technique is computationally very efficient because, once the original FSM is created, it can be used to predict the MGWV for different metal gates or grain sizes (GSs). Two state-of-the-art devices were used as test-models: a 10.7-nm gate length Si FinFET and 10.4-nm gate length In0.53Ga0.47As FinFET. The cross-sectional shape (triangular, rectangular, or bullet), the metal used in the gate (TiN or WN), and the GS (10, 7, and 5 nm) have been used as test scenarios for this technique.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
11
Top 10%
Top 10%
Top 10%
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