The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density Qinv and effective mobility μeff has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., Cof and Cf(poly-end), respectively. Both categories of parasitic capacitance lead to overestimated Qinv and underestimated μeff. The increase in effective channel width Weff due to ΔW from shallow trench isolation (STI) top-corner rounding may compensate μeff degradation due to STI stress. The tradeoff between μeff and Weff determines the impact of width scaling on IDS and Gm . A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of μeff in multifinger MOSFETs with various layouts and narrow widths down to 0.125 μm.