A simple method for determining the optimal charge balance and processing window of double-reduced surface field (RESURF) lateral devices is presented. The technique is based on the use of simple two test structures that are widely used in ICs, no special test structures are required. The optimal processing window is determined from the bounds over which RESURF is maintainable, and hence, high breakdown voltage is achievable. Using the technique, device designers can set and choose the process conditions of the device's critical layers to yield a manufacturable process prior to actual device layout, and therefore preserves the ability for layout design optimization independent of process optimization. The proposed technique also maximizes the benefits of double-RESURF processing for achieving the lowest on-resistance while maintaining the desired breakdown voltage. Using the technique, the process design and optimization guidelines for a double-RESURF LDMOS built in a high voltage IC technology are discussed and supported with experimental results.