Recent developments in non-volatile memories (NVMs) have introduced them as an alternative for SRAMs in on-chip caches. Besides the promising features of NVMs, e.g., near-zero leakage power, immunity to radiation-induced particle strike, and higher density, a major drawback of NVM-based caches is their short lifetime due to limited write endurance. This brief first reveals that in L1 caches, the lifetime of data-cache is about 472 $\times$ shorter than that of instruction-cache (I-cache) due to extreme imbalance write stress between the two. Then, we propose a technique, so-called alternating cache allocation to conduct higher endurance (A-CACHE), to improve the lifetime of frequently written D-cache by exploiting rarely written I-cache. The key idea in A-CACHE is to alternate the locations of storing instructions and data between I-cache and D-cache. The evaluation results show that A-CACHE improves the lifetime of the cache by 83% with negligible overheads.