The nested Miller compensation of three-stage amplifiers is reviewed by using a simple design-oriented approach. The method provides stable amplifiers by accurately controlling the overall phase margin as well as that of the internal loop. Furthermore, the use of nulling resistors to remove the RHP zeros is discussed and optimization criteria are described. A novel technique is presented which allows an amplifier's frequency and settling performance to be greatly improved without increasing power consumption. Thanks to the small compensation capacitors employed, the approach is amenable for integration and in particular where large load capacitors have to be driven. SPICE simulations based on a 0.8-/spl mu/m CMOS design are given and found in remarkable agreement with the theoretical analysis.