The v2.0+EDR Bluetooth SOC Architecture for Multimedia

descriptionPublicationkeyboard_double_arrow_right Article 01 May 2006 English Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Consumer Electronics, volume 52, pages 436-444 (issn: 0098-3063,

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Authors: Jeong Hun Kim; Youngwhan Choi; Jungwon Jeong; Suh Ho Lee; Suki Kim;

doi: 10.1109/tce.2006.1649661

The v2.0+EDR Bluetooth SOC Architecture for Multimedia

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Abstract

This paper proposes the advanced Bluetooth SOC architecture for multimedia applications. Our design includes baseband functions in compliance with Bluetooth core specification v2.0+EDR (enhanced data rate), RF transceiver, modem, SBC codec, ESIC processor, and power management block. This chip is SIP integration with the flash memory and occupies a die size of 28 mm/sup 2/ in CMOS 0.18 /spl mu/m. The maximum current consumption of the total chip is 65 mA. The single operation voltage of the analog and the digital parts is 1.8 V.

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