Performance analysis of double digit decimal multiplier on various FPGA logic families
Performance analysis of double digit decimal multiplier on various FPGA logic families
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of [(n/2 +1] cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard.
- Gannon University United States
- Cochin University of Science and Technology India
Carry Save Adders, Decimal Multipliers, FPGA, 004
Carry Save Adders, Decimal Multipliers, FPGA, 004
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