A fixed-throughput Wiener filter vector precoding (VP) approach specially suitable for hardware implementation in field programable gate array (FPGA) devices is introduced in this paper. The lattice decoding algorithm, which is based on the sphere decoder (SD) lattice search, performs in its first stage a reordering of the matrix to be used for the tree search. Afterwards, the search tree is configured so as to yield an appropriate BER performance, and a fixed-complexity search is carried out. Simulation results show that the BER performance of the proposed algorithm is very close to the ML solution whereas its complexity is significantly smaller than that of the SD algorithm or the exhaustive search method.