In this paper a novel algorithm for computing the Hough transform is introduced. The basic idea consists in using a combination of an incremental method with the usual Hough transform expression to join circuit performances and accuracy requirements. The algorithm is primarily developed to fit field programmable gate arrays (FPGA) implementation that have become a competitive alternative for high-performance digital signal processing applications. The induced architecture presents a high degree of regularity, making its VLSI implementation very straightforward. This implementation may be achieved by generator program, assuring a shorter design cycle and a lower cost. For illustration, implementation results of 8-bit image pixels is given.