Hardware Synthesis for Asynchronous Communications Mechanisms

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 01 Nov 2008 Spain Publisher:IEEEJournal:2008 International Conference of the Chilean Computer Science Society

Authors: Kyller Costa Gorgônio; Jordi Cortadella;

doi: 10.1109/sccc.2008.21

handle: 2117/133148

Hardware Synthesis for Asynchronous Communications Mechanisms

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Abstract

Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed concurrent processes. In this work an automatic method for synthesis of re-reading ACMs is introduced. This method is is oriented to the generation of hardware artifacts. The behavior of re-reading ACMs is formally defined and the correctness properties are discussed. Then it is shown how to generate the ACMs specifications and how they can be translated into a proper hardware implementation. Verilog has been used as the target language to describe the hardware being synthesized.

Peer Reviewed

Country

Spain

Related Organizations

Universitat Polite`cnica de Catalunya
Spain
Federal University of Campina Grande
Brazil

Keywords

Formal methods (Computer science), Communication system control, Ordinadors immersos, Sistemes d', Embedded computer systems, Metastasis, Àrees temàtiques de la UPC::Informàtica::Hardware, Read-write memory, Hardware, Verilog (Llenguatge de descripció de maquinari), Mètodes formals (Informàtica), Asynchronous communication, Pervasive computing, Verilog (Computer hardware description language), Connectors, Data communication, :Informàtica::Hardware [Àrees temàtiques de la UPC]

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