A unique circuit hardening technique is described, which can totally eliminate both alpha and neutron induced soft errors from deep submicron microcircuits. This hardening technique, termed temporal sampling, addresses both traditional static latch SEUs (single event upsets) as well as SET (single event transient) induced errors. This approach mitigates the SER (soft error rate) of modern microcircuits with minimal impact on design flow, physical layout area, and circuit performance.