Latchup in CMOS technology

descriptionPublicationkeyboard_double_arrow_right Article 01 Jan 1998Publisher:IEEEJournal:1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98

Authors: M.J. Hargrove; S. Voldman; R. Gauthier; J. Brown; K. Duncan; W. Craig;

doi: 10.1109/relphy.1998.670561

Latchup in CMOS technology

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Abstract

This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup +/ spacing.

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