Triple Module Redundancy (TMR) is a popular technique for protecting critical FPGA designs. Although automatic tools for TMR generation mostly use triplication on flip-flop level, designers may opt for different approaches. This work analyses the impact of different granularities on TMR architectures based on a coarse- and a medium-grained TMR implementation of a shared Wishbone interconnection. The actual robustness of these different implementations is measured on a Xilinx Virtex-5 FPGA by using error injection into the configuration bitstream. A specialized test setup comprising two FPGAs boards is introduced so as to allow for the execution of the robustness testing. Based on the coarse-grained architecture, a fine categorization of errors in TMR architectures can be obtained.