A physical unclonable function (PUF) with a novel hardware architecture called Pseudo-LFSR PUF (PL-PUF) is developed. The structure of the PL-PUF is based on LFSR but it actually is large combinational logic. The long feedback signal of the PL-PUF effectively extracts the device variation, and consequently the output IDs generated in the different devices become completely dissimilar. The advantages of the PL-PUF are that (1) the size of the circuit is small since it simply consists of inverters and a few XOR gates, (2) it efficiently outputs a long-bit ID since all n bits of the ID are simultaneously output from a single n-bit challenge, and (3) the challenge-response mapping of PL-PUF can be easily changed without modifying its hardware structure. The reliability of the PL-PUF is also examined in terms of False Acceptance Rate (FAR) and False Rejection Rate (FRR) through the experimentation using FPGAs. The empirical results show that the intra-device Hamming distance among IDs generated in the same PL-PUF is quite small, the inter-device Hamming distance among IDs in different PL-PUFs is sufficiently large. As a consequent, it is demonstrated that the PL-PUF has quite low FAR/FRR and is quite effective for device identification and other security-sensitive applications. This paper describes the structure of the PL-PUF in detail and presents the experimental results of the performance evaluation using Virtex-5 FPGAs.