Hardwired acceleration units capable of exploiting the parallelism of images rely on highly customized memory organizations. In this paper we analyze a widely used depth-discontinuity-algorithm applied in stereo vision systems. The main processing kernels are decomposed, and a hardwired acceleration unit is proposed for speeding up the computation. The hardware accelerator includes multiple arithmetic comparison and absolute difference units, as well as a customized memory organization. The proposed micro-organization was instantiated using a XA3S500E Spartan 3E FPGA device. The obtained results show that by implementing this new hardwired algorithm a processing acceleration of 268 times is achieved for the targeted kernel, while the solution uses 30 % of the chosen FPGA device. The baseline comparison was the pure software execution over a Microblaze soft core processor based on the same FPGA technology.