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Test method for IC electrical overstress hardness estimation

descriptionPublicationkeyboard_double_arrow_right Article 23 Nov 2002Publisher:IEEEJournal:RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294)
Authors: P.K. Skorobogatov;

doi: 10.1109/radecs.1997.698882

Test method for IC electrical overstress hardness estimation

Abstract

A test method to estimate the electrical overstress (EOS) hardness of ICs is presented. It is based on unification of test conditions. The advantage of the method is the possibility it gives to compare the EOS hardness of different ICs. A specialized test installation has been designed to estimate the hardness of different ICs to EOS, including transient and permanent effects. Experimental data for digital bipolar IC and 4K/spl times/1 CMOS RAM EOS hardness are given including the effects of upset, latch-up and catastrophic failure.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
1
Average
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