An integrated complementary MOS-transistor binary counter stage, particularly suited to low-power low-voltage applications, has been realized in monolithic form. The topology of the circuit allows one to group together all p-channel MOSTs and all n-channel MOSTs within two distinct surface areas. This feature results in an appreciable reduction of the surface necessary for a given circuit function. Dynamic current consumption is about 10 nA per kHz at a supply voltage of 1.35 volts. The complementary type of substrate is obtained by etching and epitaxially refilling wells in the original substrate material. Technological problems which had to be solved in order to achieve low-power low-voltage operation in complementary integrated MOS circuits will be discussed.