This paper summarizes a study of circuit designs for minimum power integrated electronic applications. The advantages of complementary resistor-diode-transistor logic (CRDTL) in terms of power drain, propagation delay, fan-in, fan-out and noise margin are shown. Modification of basic CRDTL design provides gate propagation delay times of 1.0 µsec with less than 250 µw power drain. Flip-flop repetition rates of 100 kc at a total power drain of 125 µw have been achieved and some designs have been operated at 6 kc and 20 µw. Additional demands on monolithic circuit fabrication imposed by micropower design are considered briefly.