The complexity of an interconnection network often determines the size of the parallel computer and thus the attainable performance of a parallel computer is limited by the characteristics of the interconnection network. Pruning technique reduces the complexity and hence increases the performance. In this paper, we apply the pruning technique on Hierarchical Torus Network (HTN) and study the architectural details of the pruned HTN. We have explored the network diameter, average distance, bisection width, peak number of vertical links, and VLSI layout area of different HTN. It is shown that the pruned HTN possesses several attractive features including small diameter, small average distance, small number of wires, a particularly small number of vertical links, and economic layout area as compared to its non-pruned counterpart.