A New architecture is presented in this paper for International Data Encryption Algorithm based on Application Specific Instruction set Processors platform. Designing process is explained comprehensively for all the main components within the crypto processor core. The basic structure is developed in order to reduce the required clock cycles for the main specific instruction which encrypts/decrypts input data. The complete instruction set is written in Register Transform Language. Then, VHDL code is utilized to test the proposed design.