A difficulty in reliability modeling is how to capture the impact of all of the various reliability defect types. The general approach to optimizing burn-in that we describe in this article addresses a multiple-defect environment. The approach has four main parts: (i) modeling the product's failure rate distribution, (ii) establishing the Pareto distribution of reliability defects, (iii) assessing the kinetic information of each reliability defect, and (iv) estimating the DPPM under product use conditions. This article compares and contrasts the acceleration effects of various extrinsic defects found in 130- and 90-nm CMOS technology products.