In-Network Cache Coherence

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 01 Jan 2006 English Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Computer Architecture Letters, volume 5, pages 9-9 (issn: 1556-6056,

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Authors: Noel Eisley; Li-Shiuan Peh; Li Shang;

doi: 10.1109/l-ca.2006.9 , 10.1109/micro.2006.27

In-Network Cache Coherence

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Abstract

We propose implementing cache coherence protocols within the network, demonstrating how an in-network implementation of the MSI directory-based protocol allows for in-transit optimizations of read and write delay. Our results show 15% and 24% savings on average in memory access latency for SPLASH-2 parallel benchmarks running on a 4times4 and a 16times16 multiprocessor respectively

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