Improving CDR Performance via Estimation
Haechang Lee; Akash Bansal; Yohan Frans; Jared Zerbe; Stefanos Sidiropoulos; Mark Horowitz;
Improving CDR Performance via Estimation
A dual-loop CDR can be viewed as a simple phase-estimator. Different estimators can be built by changing the phase DAC control logic. Three different 0.13mum estimators for a 3Gb/s serial link are presented. These estimators address dual-loop CDR limitations including lock time, frequency range, and jitter tolerance in non-mesochronous systems
- Stanford University United States
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