A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand"

T. Saeki; M. Mitsuishi; H. Iwaki; M. Tagishi

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Article . 2002 . Peer-reviewed

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A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand"

descriptionPublicationkeyboard_double_arrow_right Article 07 Nov 2002Publisher:IEEEJournal:2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

Authors: T. Saeki; M. Mitsuishi; H. Iwaki; M. Tagishi;

doi: 10.1109/isscc.2000.839733

A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand"

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Abstract

A 1.3-cycle lock time, jitter suppression clock multiplier based on direct clock cycle interpolation uses an array of short-circuit-current-suppression interpolators. The circuits are verified in 622 MHz clock and data recovery satisfying the ITU-T G.958 jitter tolerance specification.

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