A study of the referenceless CDR based on PLL

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 01 Oct 2016Publisher:IEEEJournal:2016 International SoC Design Conference (ISOCC)

Authors: JiHoon Kim; YoungJu Hwang; Yong Moon;

doi: 10.1109/isocc.2016.7799779

A study of the referenceless CDR based on PLL

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Abstract

Clock data recovery (CDR) circuit is an essential component for serial data communication. S/PDIF which is one of data coding is used. The CDR based on PLL recovers clock and data of 2.8224 ∼ 24.576MHz and was designed with the frequency detector (FD) to detect the frequency by using the preamble. The PLL, frequency detector (FD) and the reset circuits were used to design the refernceless CDR based on PLL. 65nm CMOS process is used in this study.

Related Organizations

Soongsil University
Korea (Republic of)

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