Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA
Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA
This paper focuses on the design of an improved Discrete Fast Walsh Hadamard Transform (DFWHT) domain digital image watermarking algorithm and its low complexity as well as fast hardware architecture implementation on Xilinx based (version 14.7 Virtex-7 series) FPGA with target device xc7vx1140t-1flg1930, with maximum achieved frequency of 259.202 MHz. The architecture proposed here is to our best knowledge is the first architecture for the corresponding algorithm. Both encoding and extraction algorithm have been verified using MATLAB R2013a. Both gray scale and binary watermarks are used and only gray scale cover image of maximum size (256 x 256) is used. The algorithm and the architecture is applicable for both gray scale and binary watermarks.
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