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</script>handle: 10261/195122
This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the number of faults introduced and its position in the inner state. The results obtained demonstrate the vulnerability of these implementations against fault attacks. As far as we know, this is the first time that experimental results of fault attack over Trivium are presented.
Ministerio de Economía y Competitividad TEC2013-45523- R
Ministerio de Economía y Competitividad CSIC 201550E039)
Ministerio de Economía y Competitividad TEC2010-16870
Stream Cipher, FPGA implementation, Fault attack, Trivium, Stream ciphers, Fault Attack
Stream Cipher, FPGA implementation, Fault attack, Trivium, Stream ciphers, Fault Attack
| citations This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically). | 13 | |
| popularity This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network. | Top 10% | |
| influence This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically). | Average | |
| impulse This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network. | Top 10% |
| views | 37 | |
| downloads | 17 |

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