This paper describes a new delay locked loop (DLL) architecture with infinite-skew tracking range. This is accomplished by two inverse operating delay lines, which work in a ping-pong fashion. Only a small number of delay elements are required, leading to a low delay gain and resulting in improved jitter performance compared to state of-the-art DLLs. The architecture has simple control, inherent start-up initialization, and good noise performance. The architecture is applicable for very wide frequency range while retaining good stability. It is also physically small. This architecture was designed in CMOS18 (0.18 /spl mu/m) process for 1.6 Gb/s operation.