In this paper we propose an approach of providing the best power-delay tradeoff for combinational circuits. This is done by so-called power-oriented delay budgeting which is to combine the delay-budgeting technique with aggressive power optimization. We discuss the impacts that both discrete cell library and circuit topology may have on the potential power reduction. Experimental results show that up to 65% (an average of 35%) power savings can be achieved without any delay penalty.