The precision of digital-to-analog converters (DAC) is always limited by element mismatching. These elements can be transistors, resistors, capacitors, etc. Techniques used to improve resolution often involve the sacrifice of die area. In this paper we present a design for a DAC using floating-gate MOS transistors. This approach takes the classical scaled transistor DAC techniques, where we scale our transistors by programming each transistor's floating-gate charge instead of W/L ratios. The programming eliminates device mismatch issues on DAC performance, and greatly reduces it size. A floating-gate digital-to-analog converter (FGDAC) that just occupies 37.25/spl mu/m by 18.5/spl mu/m area, was fabricated using 0.6/spl mu/m CMOS technology. Because of its small size, an array of FGDACs can be built in a single IC; a 4/spl times/4 10 bit FGDAC has been fabricated using 0.6/spl mu/m CMOS technology. Measurements show that we can obtain 7 bits of accuracy with less than 0.5LSB linearity error for a single FGDAC.