The design of a certain class of processor arrays called configurable processor arrays is studied. Unlike regular arrays, e.g. systolic/wavefront arrays, they can perform more than one single processor function and dynamically select datapaths. Therefore, processing elements have to be controlled. The concept of control flow processing elements treats control data in the same manner as operation data which are locally propagated through the array. For a certain class of algorithms an analytical procedure to specify the processing elements including the required control is given. An actual realization of a configurable processor for computations on matrices is discussed. >