As the world of computing goes more and more parallel, reconfigurable computing can enable interesting compromises in terms of processing speed and power consumption between CPUs and GPUs. Yet, from a developer's perspective, programming Field-Programmable Gate Arrays to implement application specific processors still represents a significant challenge. In this paper, we present the application of an Intermediate-Level Synthesis methodology to the design of a Gauss-Jordan elimination linear solver on FPGA. The ILS methodology takes for input a language offering an Algorithmic-State Machine programming model. Each ASM handles blocking and non-blocking connections between data-synchronized channels having streaming interfaces with implicit ready-to-send/receive signals. Using our compiler, a scalable linear solver design reaching as much as 46.2 GFLOPS was designed and tested in a matter of days, showing how the ILS methodology can enable an interesting design time/performance compromise between RTL and HLS methodologies.