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https://doi.org/10.1109/ipdps....
Article . 2013 . Peer-reviewed
Data sources: Crossref
DBLP
Conference object . 2023
Data sources: DBLP
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TM-dietlibc: A TM-aware Real-World System Library

Authors: Vesna Smiljkovic; Martin Nowack; Neboja Miletic; Tim Harris 0001; Osman S. Ünsal; Adrián Cristal; Mateo Valero;

TM-dietlibc: A TM-aware Real-World System Library

Abstract

The simplicity of concurrent programming with Transactional Memory (TM) and its recent implementation in mainstream processors greatly motivates researchers and industry to investigate this field and propose new implementations and optimizations. However, there is still no standard C system library which a wide range of TM developers can adopt. TM application developers have been forced to avoid library calls inside of transactions or to execute them irrevocably (i.e. in serial order). In this paper, we present the first TM-aware system library, a complex software implementation integrated with TM principles and suited for software (STM), hardware (HTM) and hybrid TM (HyTM). The library we propose is derived from a modified lock-based implementation and can be used with the existing standard C API. In our work, we describe design challenges and code optimizations that would be specific to any TMbased system library or application. We argue about system call execution within transactions, highlighting the possibility of unexpected results from threads. For this reason we propose: (1) a mechanism for detecting conflicts over kernel data in user space, and (2) a new barrier to allow hybrid TM to be used effectively with system libraries. Our evaluation includes different TM implementations and the focus is on memory management and file operations since they are widely used in applications and require additional mechanisms for concurrent execution. We show the benefit we gain with our libc modifications providing parallel execution as much as possible. The library we propose shows high scalability when linked with STM and HTM. For file operations it shows on average a 1.1, 2.6 and 3.7x performance speedup for 8 cores using HyTM, STM and HTM, respectively (over a lock-based single-threaded execution). For a red-black tree it shows on average 3.14x performance speedup for 8 cores using STM (over a multi-read single-threaded execution).

Peer Reviewed

Country
Spain
Keywords

Ordinadors -- Memòries, I/O, Memory allocation, Parallel programming (Computer science), Programació en paral·lel (Informàtica), Computer storage devices, System calls, Transactional memory, System library, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, :Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC]

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selected citations
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This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
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popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
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