In the current paper we investigate the factors that affect the critical charge (Q/sub crit/) for a soft error in a memory cell. Also the spread of Q/sub crit/ due to variations in the transistor model parameters is studied. The role of the current waveform that is applied in the simulation, the current pulse width, and the inclusion of back-end parasitics are discussed. Furthermore, we treat the impact on Q/sub crit/ of supply voltage, temperature, and process variant. Also, the paper deals with the effects of parameter variations through the node capacitance and the PMOS ON-current. Finally, we show the importance of the spread in Q/sub crit/ and demonstrate that detailed knowledge about the current-pulse width is necessary for accurate SER estimation.