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Development of hardware in loop for simulation accerlation

descriptionPublicationkeyboard_double_arrow_right Article 01 Dec 2012Publisher:IEEEJournal:2012 Annual IEEE India Conference (INDICON)
Authors: Snehalata S Gurav; Devi K Sumitra;

doi: 10.1109/indcon.2012.6420651

Development of hardware in loop for simulation accerlation

Abstract

The speed of the HDL simulator is the primary bottleneck of the design cycle when it comes to verification. Limiting the number of simulation tests because there is not enough time, is alarming and raises doubt about the completeness of verification. Even after doing such verification on the simulation model/RTL (behavioral) there is no hardware proof. After synthesis we will have to repeat the verification process once again. This consumes some more time.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
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