The complex IC is a novel semiconductor construct, combining trailing edge ICs with leading edge ICs to solve integration problems. Using this approach gives the IC systems designer greater flexibility in working in the world of high speed and mixed technology. Cost and manufacturing problems associated with other approaches, such as system-on-a-chip (SOC) and multichip modules (MCM) limit their market availability and affordability. Part of the cost is related to flipping the die on to a substrate, carrier or package. Besides the common issues related to CTE mismatches of materials, requiring underfill as a process, there is also the cost of designing and processing a redistribution layer on the IC. This paper discusses the manufacturing and technical attributes of using micropallet technology and flip chip wafer level processing to accomplish reliable known good die (KGD) capability for complex IC integration. The paper emphasizes the necessities required to achieve reliable fine-pitch bumping and chip placement, and also highlights some potential applications which can benefit from micropallet technology.