In this paper a new hardware implementation of the TCP protocol is presented. The design can be adapted to apply either the TCP-BIC or the TCP-CUBIC standard with an input control bit. The design was done using Verilog. It was efficiently synthesized on Faraday UMC 90 nm standard-cell library. The process of synthesizing the design was iterated multiple times with different system clock frequencies to reach an optimum result. The goal of the design was to have a positive slack and the slack time should not be too small compared to the system clock period. The maximum system clock frequency achieved was 33.3 MHz and the critical path slack was 7.28 ns which comprises about 24 percent of the clock period.