Partial-product reduction circuits (compressors) are of capital importance in the design of high performance parallel multipliers. This paper proposes compressor designs based on threshold gates which have been implemented as vMOS circuits. A typical block, a (4,2) compressor, is fully developed. Data for a (6,2) compressor are also provided. Results show that such compressors have the best performance in delay and power-delay product when compared to conventional implementations.