This paper presents the impact of gate underlap length and high-k spacer width on the parasitic capacitances of nanoscale Dual-K spacer FinFET. It was found that the optimum gate underlap length can considerably reduce the parasitic capacitances. Also, the impact of abrupt doping profile on the parasitic capacitance of the device is discussed. All the 2-D simulations were performed on 2-D Sentaurus TCAD device simulator.